Abstract

The focus of this work is to investigate the generalisation capability of compact, solid-state synapses recently proposed by the authors. The synapses can be configured to yield a static or dynamic response. Empirical models of the Post Synaptic Response (PSP), derived from hardware simulations, are developed and embedded into the neural network toolbox in MATLAB. A network of these synapses was then used to solve benchmark problems using a well-established training algorithm where the performance metric was convergence time, accuracy and weight range; the Spike Response Model (SRM) was used to implement point neurons. Results are presented and compared with standard synaptic responses.Keywords:CMOS synapses; Spiking neural networks; CMOS implementation of spiking neurons