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Krill, B, Ahmad, A, Amira, A and Rabah, H (2010) An efficient FPGA-based dynamic partial reconfiguration design flow and environment for image and signal processing IP cores. Signal Processing: Image Communication, 25 (5). p. 377. [Journal article]
Full text not available from this repository.
URL: http://dx.doi.org/10.1016/j.image.2010.04.005
DOI: doi:10.1016/j.image.2010.04.005
| Item Type: | Journal article |
|---|---|
| Faculties and Schools: | Faculty of Computing & Engineering Faculty of Computing & Engineering > School of Engineering |
| Research Institutes and Groups: | Engineering Research Institute Engineering Research Institute > Nanotechnology & Integrated BioEngineering Centre (NIBEC) > Sensors |
| ID Code: | 15856 |
| Deposited By: | Dr Abbes Amira |
| Deposited On: | 28 Sep 2010 10:21 |
| Last Modified: | 28 Sep 2010 10:21 |
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