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Walke, R.L., Smith, R.W.M. and Lightbody, G (2002) Architectures for adaptive weight calculation on ASIC and FPGA. In: Conference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers, 1999. , Pacific Grove, CA, USA , USA . IEEE. 6 pp. [Conference contribution]
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URL: http://dx.doi.org/10.1109/ACSSC.1999.831931
DOI: doi:10.1109/ACSSC.1999.831931
Abstract
We compare two parallel urray architectures for adaptive weight calculation based on QR-decomposition by Givens Rotations. We present FPGA implementations of borh orchitectures und compare them with un ASIC-bused solution. The throughput of the FPGA implementations is of the order 5-20 GigaFLOPS, making FPGA a viable alternative to ASIC implementation in applications where power consumption and volume cost ure not critical.
| Item Type: | Conference contribution (Paper) |
|---|---|
| Keywords: | QR-RLS, VLSI, VHDL, CORDIC, systolic arrays |
| Faculties and Schools: | Faculty of Computing & Engineering Faculty of Computing & Engineering > School of Computing and Mathematics |
| ID Code: | 12284 |
| Deposited By: | Dr Gaye Lightbody |
| Deposited On: | 04 Apr 2012 11:19 |
| Last Modified: | 04 Apr 2012 11:19 |
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