Ulster University Logo

Ulster Institutional Repository

Rapid design of a single chip adaptive beamformer

Biomedical Sciences Research Institute Computer Science Research Institute Environmental Sciences Research Institute Nanotechnology & Advanced Materials Research Institute

Lightbody, G, Woods, R., McCanny, J., Walke, R., Hu, Y. and Trainor, D. (2002) Rapid design of a single chip adaptive beamformer. In: Signal Processing Systems, 1998. SIPS 98. 1998 IEEE Workshop on, Cambridge, MA , USA. IEEE. 10 pp. [Conference contribution]

[img]PDF - Published Version
290b

URL: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=715791

DOI: 10.1109/SIPS.1998.715791

Abstract

This paper presents the design of a single chip adaptive beamformer which contains 5 million transistors and can perform 50 GigaFlops. The core processor of the adaptive beamformer is a QR-array processor implemented on a fully efficient linear systolic architecture. The paper highlights a number of rapid design techniques that have been used to realise the design. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilisation of alibrary of parameterisable silicon intellectual property (IP) cores, to rapidly develop the circuit layouts.

Item Type:Conference contribution (Paper)
Keywords:QR, RLS, Systolic array, VLSI
Faculties and Schools:Faculty of Computing & Engineering
Faculty of Computing & Engineering > School of Computing and Mathematics
ID Code:12271
Deposited By:Dr Gaye Lightbody
Deposited On:03 Apr 2012 09:02
Last Modified:03 Apr 2012 09:02

Repository Staff Only: item control page