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Design of a parameterizable silicon intellectual property core for QR-based RLS filtering

Biomedical Sciences Research Institute Computer Science Research Institute Environmental Sciences Research Institute Nanotechnology & Advanced Materials Research Institute

Lightbody, G., Woods, R. and Walke, R. (2003) Design of a parameterizable silicon intellectual property core for QR-based RLS filtering. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 11 (4). pp. 659-678. [Journal article]

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URL: http://dx.doi.org/10.1109/TVLSI.2003.816142

DOI: doi:10.1109/TVLSI.2003.816142

Abstract

The availability of an intellectual property core for recursive least squares (RLS) filtering could enable the RLS algorithm to replace the least mean squares algorithm in a wide range of applications. The goal of this study is to develop a parameterizable generic architecture for RLS filtering in the form of a hardware description language (HDL) description, which can be used to generate highly efficient silicon layout. The key issue is to develop a family of circuit architectures that are 100% efficient and locally connected. This paper presents a generic mapping for RLS filtering and circuit architectures that can be mapped to a range of application requirements. It outlines the transition from array to architecture covering detailed design issues such as timing and control generation. The result is a family of QR designs, which are parameterized in terms of architecture size, wordlength, performance, and arithmetic processor timing.

Item Type:Journal article
Keywords:Arithmetic , Circuits , Filtering algorithms , Hardware design languages , Intellectual property , Least mean square algorithms , Least squares methods , Resonance light scattering , Silicon , Timing
Faculties and Schools:Faculty of Computing & Engineering
Faculty of Computing & Engineering > School of Computing and Mathematics
ID Code:12261
Deposited By:Dr Gaye Lightbody
Deposited On:03 Apr 2012 09:16
Last Modified:03 Apr 2012 09:16

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